In recent years, with the increase in the speed of information communications, the increase in the speed of an optical disc pick-up and the increase in the capacity, there is an increasing demand for an A/D converter with a high speed and a wide input bandwidth, which also has a reduced area and a reduced power consumption in order to reduce the cost.
FIG. 14 shows a configuration of a conventional parallel-type A/D converter 1400. A high-speed analog/digital conversion was realized by using this A/D converter.
The A/D converter 1400 includes a reference voltage generation circuit 1401, a chain of differential amplifiers 1402, a chain of comparators 1404, and an encoder circuit 1405. The reference voltage generation circuit 1401 divides the voltage between a high voltage-side reference voltage 1401a and a low voltage-side reference voltage 1401b by a plurality of resistors R1 to Rn to generate reference voltages VR1 to VRn+1. The reference voltages VR1 to VRn+1 are input to the chain of differential amplifiers 1402. The chain of differential amplifiers 1402 includes n+1 differential amplifiers and performs predetermined amplification operations in parallel on the relationships between the analog input signal voltage received from an analog input signal voltage input terminal AIN and the reference voltages VR1 to VRn+1, the results of which are input to the chain of comparators 1404. The chain of comparators 1404 compares in parallel the outputs of the chain of differential amplifiers 1402. The encoder circuit 1405 logically processes (converts) the comparison results output from the chain of comparators 1404 to thereby output a digital signal DOUT of a predetermined resolution. Where the number of bits of the A/D converter is denoted as N, n is about 2 to the power of N.
A conventional A/D converter having a parallel configuration as described above is advantageous in that the reference voltages and the analog input signal voltage can be simultaneously subjected to the comparison process in parallel, thus realizing a high-speed A/D conversion, as compared with those of the integrating type or the series parallel type.
However, there is a disadvantage that in order to increase the resolution of the A/D converter by one bit, it is necessary to double the number of differential amplifiers and the number of comparators, thus increasing the power consumption and the occupied area. Moreover, there is another disadvantage that increasing the resolution of the A/D converter increases the level of required specifications such as the offset error and the gain of the differential amplifiers, and the offset error and the comparison precision of the comparators.
Patent Document 1 discloses an A/D converter with improvements to disadvantages as set forth above.
FIG. 15 shows an exemplary configuration of another conventional parallel-type A/D converter 1500 with improvements to disadvantages of parallel-type A/D converters as set forth above. The A/D converter 1500 includes a reference voltage generation circuit 1501, a chain of differential amplifiers 1502, a chain of interpolation resistors 1503, a chain of comparators 1504, and an encoder circuit 1505. The structure of the A/D converter 1500 is similar to that of the A/D converter 1400 of FIG. 14 with respect to the chain of comparators and the encoder circuit, but differs therefrom with the smaller number of resistors included in the reference voltage generation circuit 1501, the smaller number of differential amplifiers included in the chain of differential amplifiers 1502, and the provision of the chain of interpolation resistors 1503.
The reference voltage generation circuit 1501 divides the voltage between a high voltage-side reference voltage 1501a and a low voltage-side reference voltage 1501b by m resistors R1 to Rm, being fewer than 2 to the power of N (N: the number of bits of the A/D converter), to generate reference voltages VR1 to VRm+1. The reference voltages VR1 to VRm+1 are input to the chain of differential amplifiers 1502. The chain of differential amplifiers 1502 includes m+1 differential amplifiers and performs predetermined amplification operations in parallel on the relationships between the analog input signal voltage received from an analog input signal voltage input terminal AIN and the reference voltages VR1 to VRm+1, the results of which are input to the chain of interpolation resistors 1503. The chain of interpolation resistors 1503 includes a plurality of resistors, and divides the differential voltage between the positive terminal output voltage and the negative terminal output voltage of two adjacent differential amplifiers and the differential voltage between the negative terminal output voltage and the positive terminal output voltage thereof, obtaining the results as differential interpolated voltages, which are given to the chain of comparators 1504. The chain of comparators 1504 compares in parallel the interpolated voltages. The encoder circuit 1505 logically processes (converts) the comparison results output from the chain of comparators 1504 to thereby output a digital signal DOUT of a predetermined resolution.
Where the number of bits to be interpolated is denoted as L bits, it is possible with the A/D converter 1500 to reduce the number of differential amplifiers to 1/L of that of the conventional A/D converter 1400. Therefore, it is advantageous in that it is possible to reduce the power consumption and the area. However, as with the conventional A/D converter 1400, there is a disadvantage that in order to increase the resolution of the A/D converter by one bit, it is necessary to double the number of comparators, thus increasing the power consumption and the occupied area. Moreover, as with the conventional A/D converter 1400, there is another disadvantage that increasing the resolution of the A/D converter increases the level of required specifications such as the offset error and the comparison precision of the comparators.
Patent Document 2 discloses an A/D converter with improvements to disadvantages as set forth above.
FIG. 16 shows an exemplary configuration of another conventional parallel-type A/D converter 1600 with further improvements to disadvantages of parallel-type A/D converters as set forth above. The A/D converter 1600 includes a reference voltage generation circuit 1601, a chain of differential amplifiers 1602, a chain of comparators 1604, and an encoder circuit 1605. The structure of the A/D converter 1600 is similar to that of the A/D converter 1500 of FIG. 15 with respect to the reference voltage generation circuit 1601, the chain of differential amplifiers 1602 and the encoder circuit 1605, but differs therefrom with the absence of the chain of interpolation resistors 1503, and the inputs to the chain of comparators being positive terminal and negative terminal output voltages of two adjacent differential amplifiers.
The reference voltage generation circuit 1601 divides the voltage between a high voltage-side reference voltage 1601a and a low voltage-side reference voltage 1601b by m resistors R1 to Rm, being fewer than 2 to the power of N (N: the number of bits of the A/D converter), to generate reference voltages VR1 to VRm+1. The reference voltages VR1 to VRm+1 are input to the chain of differential amplifiers 1602. The chain of differential amplifiers 1602 includes m+1 differential amplifiers and performs predetermined amplification operations in parallel on the relationships between the analog input signal voltage received from an analog input signal voltage input terminal AIN and the reference voltages VR1 to VRm+1, the results of which are input to the chain of comparators 1604. Each comparator included in the chain of comparators 1604 is given the positive terminal and negative terminal outputs of two adjacent differential amplifiers. The input transistor of each comparator is formed with a predetermined size ratio and compares, while performing interpolation, the positive terminal and negative terminal outputs of two adjacent differential amplifiers in parallel and in synchronism with a clock signal CLK. Note that the interpolation operation does not require interpolation resistors. The encoder circuit 1605 logically processes (converts) the comparison results output from the chain of comparators 1604 to thereby output a digital signal DOUT of a predetermined resolution.
FIG. 17 shows an exemplary configuration of a dynamic-type comparator 1700 used in the chain of comparators 1604 of the parallel-type A/D converter 1600 shown in FIG. 16. The comparator 1700 includes an input transistor section including NMOS transistors m11, m12, m21 and m22, and a positive feedback section (cross-coupled inverter latch section) including NMOS transistors m1a and m1b and PMOS transistors m3a and m3b, wherein an output terminal QB is connected to the gate terminals of the NMOS transistors m1a and m3a and the drain terminal of the PMOS m3b of the positive feedback section, and an output terminal Q is connected to the gate terminals of the transistors m1b and m3b and the drain terminal of the PMOS transistor m3a of the positive feedback section. An NMOS transistor m2a functioning as a switch in synchronism with the clock signal CLK is connected between the drain terminal of the NMOS transistor m1a and the drain terminal of the PMOS transistor m3a, and an NMOS transistor m2b functioning as a switch in synchronism with CLK is connected between the drain terminal of the NMOS transistor m1b and the drain terminal of the PMOS transistor m3b. The source terminals of the PMOS transistors m3a and m3b are connected to the power supply VDD. A PMOS transistor m4a functioning as a switch in synchronism with the clock signal CLK is connected between the drain terminal of the PMOS transistor m3a and the power supply VDD, and a PMOS transistor m4b functioning as a switch in synchronism with CLK is connected between the drain terminal of the PMOS transistor m3b and the power supply VDD.
The positive terminal output Vo1 and the negative terminal output Vob1 of the first differential amplifier and the positive terminal output Vo2 and the negative terminal output Vob2 of the second differential amplifier are connected to the gate terminals of the NMOS transistors m11, m21, m12 and m22, respectively, of the input transistor section, and the reference ground potential VSS is connected to the source terminals thereof. The drain terminals of the NMOS transistors m11 and m12 are connected to the source terminal of the NMOS transistor m1a (hereinafter referred to as a “node Va”), and the drain terminals of the NMOS transistors m21 and m22 are connected to the source terminal of the NMOS transistor m1b (hereinafter referred to as a “node Vb”). The gate terminals of the NMOS transistors m2a and m2b functioning as switches in synchronism with the clock signal CLK and the gate terminals of the PMOS transistors m4a and m4b functioning as switches in synchronism with the clock signal CLK are both connected to the clock signal CLK.
The input transistor section performs a predetermined weighting operation to thereby determine the threshold voltage Vtn, and outputs, to the positive feedback section, comparison results obtained by comparing the difference voltage between the positive terminal output voltage Vo1 and the negative terminal output voltage Vob1 of the first differential amplifier and the difference voltage between the positive terminal output voltage Vo2 and the negative terminal output voltage Vob2 of the second differential amplifier. The predetermined weighting operation is realized by, for example, setting the size ratio of the gate width W of the transistors of the input transistor section to a fixed value. For example, the threshold voltage Vtn can be obtained by setting the size ratio between the size of the transistor m11 and the size of the transistor m12 to 1:3 and the size ratio between the size of the transistor m12 and the size of the transistor m22 to 1:3.
In the positive feedback section, when the clock signal CLK is greater than or equal to a predetermined level (hereinafter referred to as being “high”), the PMOS transistors m4a and m4b are opened (OFF) and the NMOS transistors m2a and m2b are closed (ON), thus amplifying the comparison result output from the input transistor section, and the amplified comparison result is stored and output as a digital signal.
When the clock signal CLK is less than or equal to a predetermined level (hereinafter referred to as being “low”), the PMOS transistors m4a and m4b are closed (ON), and the output terminals Q and QB are reset to the power supply voltage VDD, i.e., “high”. Moreover, the NMOS transistors m2a and m2b are opened (OFF), thus disconnecting the current path, whereby the power consumption becomes zero.
Thus, the transistors included in the input transistor section of the comparator have an arbitrary size ratio (i.e., the transistors are weighted), thereby advantageously eliminating the need for the chain of interpolation resistors used in conventional techniques. Moreover, this makes it possible to save the operation current and the area required for the interpolation circuit, thus advantageously reduce the power consumption and the area. Moreover, being a dynamic-type comparator, it also provides an advantage that the power consumption is reduced.
Patent Document 1: Japanese Laid-Open Patent Publication No. 4-43718
Patent Document 2: Japanese Laid-Open Patent Publication No. 2003-158456